Method for producing a tensioned layer on a substrate, and a layer structure

ABSTRACT

The invention relates to a method for producing a tensioned layer on a substrate involving the following steps: producing a defect area in a layer adjacent to the layer to be tensioned, and; relaxing at least one layer adjacent to the layer to be tensioned. Additional layers can be epitaxially deposited. Layer structures formed in this manner are advantageously suited for components of all types.

The invention relates to a method of making a strained layer on asubstrate as well as to a layer structure.

The rapid advance in nanoelectronics has required increasingly morerapid transistors, especially metal oxide field effect transistors(MOSFETs). A power increase is as a rule obtained with a reduction inthe transistor dimensions. This is, however, very expensive anddifficult to achieve since the key technologies in chip production, likethe lithographic process and the etching process must be replaced bysystems capable of greater outputs.

An alternative approach is the use of materials capable of greateroutputs. Instead of the usual silicon substrates, increasingly so-calledsilicon on insulator (SOI) substrates are used. In those cases, beneatha monocrystalline silicon surface a buried silicon oxide (SiO₂) layermay be provided with insulating characteristics. Electronic components,especially MOSFETs (metal oxide silicon field effect transistors) havewith SOI substrates more rapid switching operations and reduced losses.These substrates are commercially available and are made either by ionimplantation of oxygen in silicon and heat treating (the so-called SIMOXprocess, SIMOX wafer) or by means of bonding of two oxidized wafers andsplitting or back etching a part of the second wafer (the so-calledWafer Bond process). The thus made wafer is referred to as a BESOI wafer(bonded and etch back SOI).

It is known also to use strained silicon (strained silicon-germaniumalloys (Si—Ge) alloys or silicon-carbon (Si—C) andsilicon-germanium-carbon (Si—Ge—C). The use of silicon or Si—Ge, Si—C orSi—Ge—C in certain elastic dislocation states or distorted states,improves the material properties especially with respect to the chargecarrier mobility of electrons and holes which are primarily importantfor electronic components. The use of these and other high valuematerials enables a performance enhancement of Si based high powerelectronic components like MOSFETs and MODFETs without the need toreduce the critical structural dimensions of the electronic components.Such elastically strained layer systems enable epitactic growth onspecial substrates or on stress relaxed layers and so-called virtualsubstrates whose production with reduced defect densities is veryexpensive and difficult (F. Schaeffler, Semiconductor Sci. Techn. 12(1997) pages 1515-1549).

The production of monocrystalline layers with substrate materials whichare currently available is greatly limited or the quality of the layersgrown is reduced. Different crystal structures as well as differentlattice parameters between the substrate and the layer material (latticemismatch) reduce as a rule the ability for monocrystalline growth oflayers of the higher quality. When monocrystalline layers are depositedon surfaces or bodies with lattice parameters which are not matched tothose of the monocrystalline layer, the monocrystalline layer developsfrom the beginning in a stressed state since its lattice structurediffers in this state from that of the substrate. If the deposited layerexceeds a so-called critical layer thickness, the mechanical stressundergoes dislocation formation as it tends toward relief and thelattice structure becomes closer to the original or to that of thesubstrate. This process is referred to as stress relaxation and in thefollowing as relaxation. At the interface so-called lattice mismatchdislocations (misfit dislocations) can arise and in the relaxed layerare in the form of threading dislocations which run from the surface ofthe layer to the interface. The misfit dislocations are required forstress relaxation and do not degrade the layers lying thereabove. From acertain lattice mismatch (about >0.5%) the threading dislocation densityis so high, however, that such layers maybe unsuitable for electroniccomponents. In general, the threading dislocation density can besomewhat reduced by a temperature treatment. Under the term dislocationdensity or defect density, the threading dislocation density is to beunderstood here. Since most of the dislocations either advance throughnewly grown layers, they may reduce the electrical and opticalcharacteristics of these layers significantly.

Since the silicon-germanium (Si—Ge) material system is thermodynamicallya fully miscible system, the compound can be produced in optionalconcentrations in either silicon or germanium. Silicon and germaniumindeed are characterized by the identical crystal structure althoughthey differ with respect to the lattice parameter by about 4%, that isan Si—Ge layer or a pure Ge layer will grow in a strained state onsilicon. Carbon can be incorporated into silicon in an amount up toabout two atomic % in a substantial inclusion so as to reduce thelattice parameter.

The state of the art in the production of strained silicon on stressfree qualitatively high value silicon-germanium alloy layers on asilicon substrate is the use of the so-called graded layer on which thedesired strained layer is deposited in a further step. The graded layercan be a silicon-germanium layer whose germanium concentration increasescontinuously to the surface until it reaches the desired germaniumcontent continuously or in a stepwise manner. Since, to maintain thelayer quality, only an increase in the germanium content of about 10atomic % per μm is required, such layers depending upon the germaniumconcentration to be achieved, can be up to 10 micrometer thick. Thelayer growth of this graded layer is described in (Thin Solid Films, 294(1997), 3 to 10).

This process gives rise, as a drawback, to excessively high layerroughnesses, to dislocation multiplication and thus to a bundling ofthreading dislocations which can develop in such manner as to make theelectronic components to be made from the layers nonfunctional.

In addition, there can be a tipping or tilting crystallographically ofcertain regions so that an expensive polishing operation of the layer,for example by means of chemical mechanical polishing techniques isrequired before strained silicon can be deposited on the thus producedbuffer in an additional epitaxial growing step.

Before this second layer deposition in a CVD reactor or in a molecularbeam epitaxy apparatus, a special wafer cleaning must also be carriedout to insure a monocrystalline growth and to minimize the inclusions ofimpurities or undesired doping substances. The many process steps, amongothers, a lengthy deposition process as a consequence of the large layerthicknesses required, expensive polishing, wafer cleaning and twoseparate epitaxy steps, reduce the output or productivity of the processand limit the quality. The thermal conductivity of such graded layers isso sharply reduced by comparison to silicon that high power electriccomponents rapidly are overheated.

Indeed, from Leitz, et al, Applied Physics Letters, Vol. 79(25) (2001),pages 4246-4248) and Cheng et al (Mat. Res. Soc. Symp., Vol. 686 (2002)A1.5.1-A1.5.6 it is known that a stress relaxed or a strained layer canbe transferred to a second wafer with wafer bonding. The disadvantage ofthis approach is, however, that very many technically difficult stepsare required. A stress relaxed layer or also only a single strainedsurface layer can thus be bonded to an insulating SiO₂ layer on thesecond wafer. Among other things, it is exceptionally problematical totransfer the strained layer by wafer bonding to a second substratewithout altering the elastic strain of the layer and in such manner asto avoid the inclusion of impurities. Impurities, for example at theinterface of the strained silicon with the SiO₂ increase in anundesirable manner the interface state density. Even the smallestimpurity level can effect the switching properties of MOSFETs which areformed on the strained silicon in a highly detrimental manner. Preciselywith MOSFETs with ultrathin strained silicon the interface state densityshould be in the range of 10¹⁰ cm⁻² at the Si/SiO₂ interface.Technologically, this can be achieved only with ultrapure interfaces.Whether this wafer bond process can satisfy this requirement has not yetbeen shown.

From R. Delhouge, P. Meunier-Beillard, M. Caymax, R. Loo, W. Vanderhorst(First Int. SiGe Technology and Device Meeting (ISTDM2003), Jan. 15-17,2003, Nagoya, Japan, page 115) it is known that thin relaxed Si—Gelayers can be produced by forming in an SiGe layer (for example 170nanometer Si—Ge with 22 atomic % Ge) a very thin (for example 10nanometer) Si—C layer with a sufficiently high carbon content. Duringthe heat treatment at elevated temperatures of about 1000° C. carbonprecipitates out as a result of supersaturation. In this manner defectsare formed which promote the relaxation of an Si—Ge layer.

It is a disadvantage that in this manner no strained layer can be formedon an insulator. The surface roughness makes polishing necessary as arule. Furthermore, a high temperature is required for the relaxationsince the high temperature is made necessary by the precipitation ofcarbon and thus lower temperatures cannot be used.

From W099/38201, a method is known which permits the production of athin stress-relaxed Si—Ge buffer layer by means of ion implantation andthermal treatment. A drawback of this method is that with it, nostrained layer can be directly produced on a substrate. As aconsequence, two separate epitaxial deposition and wafer cleaning stepsare required.

The object of the invention is thus to provide a simple method of makinga strained layer of high quality on a substrate without wafer bondingand/or wafer polishing.

Especially in an advantageous mode, strained silicon should be directlyapplicable of an SOI wafer over its entire surface or locally and in anoptional form. In local application, the planarity between the strainedand nonstrained response should be free from any step formation toenable the further processing of electronic components.

It is an object of the invention, further, to provide electronic and/oroptoelectronic components which have the above mentioned advantageouslayer structures.

The objects of the invention are achieved with a method according to themain claim. The objects are achieved further by a layer structureaccording to the auxiliary claim. Advantageous modes and features arefound in the patent claims which are respectively dependent thereon.

According to the main claim, to produce a strained layer on a substrate,the following steps are carried out:

generating defects in a layer adjoining the layer to be strained,

relaxing at least one of the layers adjoining the strained layer.

For this purpose, the layer structure is subjected to at least onethermal treatment and/or an oxidation so that starting from the defects,dislocations are formed which give rise to a relaxation of one of thelayers neighboring the strained layer.

As a consequence, the straining of the layer to be formed as a strainedlayer is advantageously effected.

Under the term “defect”, crystal defects are to be understood, thatmeans atomic and extended defect locations, for example, clusters,bubbles, hollows and the like. Starting from such generated defectregions, dislocations are formed which give rise to a relaxation of alayer. neighboring the layer to be formed as the strained layer.

Under “relaxation” an abatement of the elastic stress within a layer isto be understood.

The term “neighboring layer” is to be understood as referring to a layerwhich may be directly adjacent the layer to form the strained layer orto one or more layers separated therefrom to the extent that therelaxation of dislocations therein gives rise to the strained layer.

The term “substrate” is used in the broadest sense to refer to a layeron which the strained layer can be provided. In the course of theinvention, it is possible to provide additional layers on the substrateas well.

On the free surface of the strained layer or the layer to be thestrained layer, epitactically at least one first layer can be applied,whereby this first layer has a different degree of stress than the layerto form the strained layer.

In the first layer, therefore, defects can be generated. The layerstructure is subjected to at least one temperature treatment so thatstarting from the defects, dislocations will be formed which lead torelaxation of the first layer. As a consequence thereof, the layer belowwhich is to be the strained layer is thereby strained.

The defects also can be self generating also in the layer to form thestrained layer.

As in the first layer, a graded layer is also to be understood withwhich, when the graded layer is in the vicinity of the layer to form thestrain layer, it has a different degree of stress than the layer to formthe strain layer. Thus, in the graded layer a defect region is produced.The layer structure is then subjected to a thermal treatment so thatstarting from this defect region, dislocations are formed which giverise to a relaxation of the region of the graded layer in the vicinityof the strained layer. As a consequence, the strain will transmit to thebounding layer intended to form the strained layer.

In the course of the method of the invention, the layer intended to formthe strained layer is formed into an elastically strained layer. To thisend, the layer bounding on the strained layer to be formed relaxes,thereby insuring advantageously a transition of the layer to be strainedinto the desired strained state. In the case of a graded layer as thefirst layer, the layer region of the graded layer which bounds upon thestrained layer relaxes so that the strained layer is transformed intothe desired strained state. The layer disposed upon the layer which isto form the strained layer has a different degree of stress than thelayer to form the strained layer itself.

In the course of the method, the deposition of additional layers ispossible.

Thus, it is possible to carry out the method with the following steps:

on a layer to form the strained layer on a substrate, at least one firstlayer of a different lattice structure is deposited and a second layerdeposited on the first layer, whereby the first layer has a differentdegree of stress than the layer to form the strained layer,

in the second layer and/or in a further layer a defect region isproduced,

the layer structure is subjected to a thermal treatment so that startingfrom the defect region dislocations are formed which contribute torelaxation of the first layer.

The first relaxing layer borders upon the layer which is intended toform the strained layer and as a consequence, causes that layer to be astrained layer.

When different lattice structures for the layers are described, it ismeant that they have a difference in the respective lattice parametersand/or in the crystal structure.

According to the invention, between a layer adapted to form the strainedlayer and the substrate, a further layer which is also relaxed in thecourse of the process can also be arranged. In that case, one obtains arelaxed layer on a substrate upon which a layer to form the strainedlayer is arranged. On the latter, in the further course of the method, arelaxing layer is applied. Upon this relaxing layer can a layer adaptedto form a strained layer, be applied. Further layers can then be appliedthereto. The relaxing layers have a different degree of stress than theneighboring layers which are to form the strained layer. Afterrelaxation of the layers, the layer adapted to form the strained layeris strained in a method step during the thermal treatment or during theoxidation.

The defect region can also be produced in the substrate. The defectregion is so produced that the dislocations give rise to a relaxation ofa neighboring layer to the layer adapted to form the strained layer.

Such an epitactic layer structure or wafer can advantageously be made ina deposition process. It is especially advantageous when the wafer isintroduced into the reactor and can be coated without expensivepolishing and cleaning operations.

By the choice of the stress of the layer to be applied to the layeradapted to form the strained layer, namely, whether that stress is atension stress or a compression stress, the resulting stress is selectedfor the layer adapted to form the strained layer.

So that the relaxation of a strained layer and thus a strain can beapplied to the layer to be strained, the layer structure isadvantageously subjected to a thermal treatment. It is, however, alsoconceivable in place of a temperature treatment to use another treatmentso that a neighboring layer will be relaxed and the layer is strained.

It is especially advantageous to carry out the relaxation by means of anoxidation with O₂ or water vapor [steam]. Instead of a purely thermaltreatment to form the relaxed region, an oxidation treatment can becarried out thereafter or, also a combination of oxidation and thermaltreatment can be used. In this case, the concentrations of the elementsare important for the functionality of the electronic component, can beincreased within the layer structure (for example, there can be a Geenrichment of the Si—Ge).

The substrate is preferably an SOI substrate whose silicon surface isstrained.

As to the substrate generally, an amorphous layer, of especially aninsulator, can also be used. The substrate can, however, equally well bea material with optional electrical characteristics which permits athermally induced stressing of the layer to form the strained layer withthe aid of the method according to the invention. In this sense, acrystalline hetero interface with a sufficiently large lattice mismatch(for example 1%) or with different crystal structures is suitable whenthe layer thickness d₃ of the layer to form the strain layer is selectedto be sufficiently small (for example 5 to 50 nm) and the substratesufficiently thick, for example 10 to 100 times the thickness of the tobe strained layer. These conditions are fulfilled for example by amonocrystalline SOI substrate, silicon on sapphire.

Also suitable are substrate materials which at the temperatures requiredfor relaxation, become Viscous. For example, silicon dioxide (SiO₂)become viscoelastic at temperatures of about 950° C. By means of borondoping SiO can be made viscoelastic already at about 800° C.

In this sense, other temperature resistant glasses are also suitable.Such substrates can be made by wafer bonding, in a manner similar tothat for commercial BESOI substrates whereby a thin Si layer is bondedto silicon dioxide. The putative strain layer that is the layer to betransformed into the strained layer, can thus in principle be applied toa suitable optional glass or another appropriate temperature resistantsubstrate. With corresponding thicknesses of these materials, they canalso fulfill the functions of a suitable mechanical support for thelayer structure. A certain bendability of the substrate is also desiredin conjunction with the development of “flexible electronics”.

As materials for the substrate, especially for example Si—C, graphite,diamond, quartz glass, Gd Ga garnet as well as III-V semiconductorsIII-V nitrides fall within the considerations.

The process according to the invention has a number of advantages.

Advantageously, this process enables the production of a strain layeronly through an epitaxial deposition and without expensive and timeconsuming process steps like wafer bonding and polishing (CMP).

It is also an advantage that commercially available SOI structures,BESOI wafers or SIMOX wafers with a thin silicon surface adapted to formthe strain layer can be used as the base. The silicon layer of thiswafer is then strained during the process. SIMOX wafers have generally adislocation density of about 10⁻⁵ cm⁻², more usually 10²-10³ cm⁻² butshow good layer homogeneity and purity as well as economicalfabrication.

The method utilizes process steps which have become established insilicon technology. The technology can also be transferred to very largewafers, for example 300 mm wafers.

The defect region can be produced by ion implantation.

In a further development of the invention it is also possible to producethe defect region already with the application of the layers to theputatively strained layer, for example by reducing the temperature, forinstance to about 200° C., in a molecular beam epitaxy apparatus duringthe deposition of the layer or of a graded layer upon the layer to formthe strained layer.

In a further advantageous feature of the invention, the defect regioncan be produced by incorporating an Si—C layer.

In a further features of the invention, for the thermal treatment, as asuitable parameter, a temperature is selected which lies between 550° C.and 1200° C. and especially between 700° C. and 950° C. In this case,starting from a defect region in the first and/or second layer, defectsand especially dislocations which can give rise to a relaxation of thefirst layer are formed as a result of which the putative strain layercan be strained.

By the choice of the stressing of the first layer, tension stresses orcompression stresses can be selected and the resulting strain in theputative strain layer can be selected. If the first layer prior to thetemperature treatment is under compressive stress, for example, by theselection of Si—Ge as the material for the first layer (with an optionalGe concentration,) then the layer which is to be provided with thestrain, for example, comprised of silicon, will have a tensile strainimparted thereto.

Conversely, compression-strained silicon can be produced for example bythe use of a first layer under tensile stress and, for example, of Si—Cwith up to about 1 to 2 atomic % C. The use of ternary alloys likeSi—Ge—C and the use of doped Si layers or alloys (B, As, P, Sb, Er, S orothers) is also possible.

The thermal treatment can be carried in an inert atmosphere, vacuum oralso in an oxidizing environment, for example, in O² or H₂O, or in anitriding atmosphere, for example, in NH₃, or a reducing atmosphere, forexample, in former gas. Very good results are obtained with thermaltreatment in nitrogen.

The so produced strained layer can be exposed, for example, by wetchemical removal of the second layer and then at least partially of thefirst layer. This layer structure serves to allow complex layerstructures to be built up. For this purpose, the skilled worker in theart can use all available processing techniques and layering materialsdepending upon the layer structure to be formed and the particularrequirements the layer structure is to satisfy.

As starting structures, as has been noted, basically SOI structures,SIMOX wafers or BESOI structures can be used. In these cases, the layerto be formed into the strained layer, the insulator and the substratewill already be available as the basic structure.

It is, however, possible to apply the layer to form the strained layerinitially to an amorphous layer, for example, an insulator forming theamorphous layer and then generate the strain. The insulator can bedisposed on a substrate, for example, of silicon or can form thesubstrate itself. The layer to be strained can advantageously besilicon. The clear to be strained can especially advantageously beformed with a thickness of 1 to 100 nm, especially of 5 to 30 nm. Thislayer thickness d₃ should at least not exceed the critical layerthickness and must be so small that at least a substantial part of thedislocations from the first layer can spread along the slide planes inthis layer. This technique depends especially upon the degree of stressin the first layer and its layer thickness d₄. The larger the desiredstress of the layer the smaller must d₃ be. A large layer thicknessratio of d₄/d₃ appears to be advantageous, especially a layer thicknessratio of d₄/d₃ of greater than 10.

In an especially advantageous feature of the invention as the firstlayer upon the layer to form the strained layer should be for example anepitactic Si—Ge or Si—Ge—C or Si—C layer with a thickness close to thecritical thickness. The critical layer thickness defines the maximumlayer thickness for this first layer at which a defect free growth isstill possible on the nonlattice matched layer to ultimately from thestrained layer. At a layer thickness below this critical layer thicknessas a rule strongly pseudomorphic that is completely defect free growthwill be produced. The critical layer thickness should not be exceeded tothe extent that the layer will already be noticeably relaxed.

As an alternative to a layer with constant composition, the graded layercan be used. The composition can rise or fall within the graded layer.In the case of Si—Ge, the concentration can slowly rise or rise in stepsor it can commence with an higher germanium concentration or even withpure germanium (Ge) over only several nanometers. If in spite of this asufficient layer thickness d₄ must be maintained without exceeding thecritical layer thickness, the Ge concentration can rapidly drop (forexample to 25 atomic %). Under this selected condition, the layerthickness can lie at about 80 nanometers. The region with the higher Geconcentration enables high degrees of relaxation in excess of 80%.

A U-concentration profile can also be of advantage to produce a certainGe concentration of, for example, 20 to 40 atomic % and the greatestpossible degree of relaxation of the first layer and thus a high degreeof strain in the layer to which the strain is to be imparted.

It is thus advantageous to select a thickness d₄ of the first layerwhich is as large as possible consistent with efficient stressrelaxation.

With a constant Ge concentration of 20 atomic % Ge a maximum thicknessof about 400 nanometers can be produced. A complex concentration profileis of advantage with higher Ge contents.

In a further feature of the invention, the second epitacticallydeposited layer can be made from epitactic silicon. This layer thenserves to form a defect region. The layer thickness d₅ of this layer canbe optimized for the formation of the defect region. It is not limitedby growth criteria. The thickness d₅ can thus be freely varied (forexample from 0 to 1000 nanometers). Advantageously, a thickness of about200 to 500 nanometers is used with hydrogen and helium implantation. Thethinnest possible layer enables implantation with low energies (forexample 10 kev) and thus with a sharper distribution of the implantedions as is advantageous for the formation of a thin defect region with aconstant cost saving.

Optionally, a further layer is also deposited, for example, to avoidsurface roughening by blistering after hydrogen or helium implantationupon the second layer. This further layer can be amorphous or apolycrystalline layer. This further layer can be deposited before orafter the generation of the defect region, for example, by ionimplantation. The layer thickness of this optional layer need bedetermined only by the implantation parameters.

The materials and techniques of the individual layers given here aregiven by way of example only and should not be understood to be alimitation of the invention.

In an especially advantageous feature of the invention by arranging amask on the second or optional further layer, a locally limited defectregion is produced. It is especially advantageous in this connectionthat the layer which is to become the strained layer should have planarregions which may be locally strained and unstrained, that is regionswhich are strained and unstrained in a plane directly adjacent oneanother without step formation between them as has been the case withthe techniques known in the art.

The defect region or regions can be made especially advantageous by ionimplantation using light ions like hydrogen (H⁺, H₂ ⁺) helium, fluorine,boron, carbon, nitrogen, sulfur, and so forth, or using ions of thelayer material or the substrate materials themselves, and thus forexample silicon or germanium in an Si/Si—Ge-Heterostructure in suchmanner that the ions are primarily implanted in the second layer.

It is advantageous to use ions which avoid undesired contamination ordoping of the structure. In this case, inert gas ions, for example, Ne,Ar, Kr, etc. are usable.

For hydrogen or helium ions a dose of about 3×10¹⁵ to 3.5×10¹⁶ cm−² andespecially for helium of 0.4×10⁶ to 2.5×10¹⁶ cm⁻² is used. A combinationof two implantings, for example the first being hydrogen and the secondbeing helium or the first being boron and the second being hydrogen, canbe suitable. A boron implantation in combination with hydrogenimplantation permits the hydrogen implantation dose to be reduced. Inaddition, a thermal treatment between the implantation steps can beadvantageous to produce nucleation seeds for the defect formation.

The defect region is advantageously formed at a distance of 50 to 500 nmfrom the layer to be relaxed.

In the case of hydrogen or helium ions, the energy of the ions and themain range of the ions is so selected that they are implanted at adistance d₆ from the interface of the first and second layers. Thisdistance d₆ lies, for example, in the range of 50 to 300 nm. For heavierions and/or larger layer thicknesses of the second layer, these limitscan also be exceeded.

If there is only one layer with a constant concentration (or a gradedlayer) applied to the layer to form the strained layer, it is possiblefor the artisan with few and simple tests to so arrange the defectregion that after the thermal treatment the first layer will be relaxedand the layer to be strained will have the requisite strain.

The implantation depth is matched to the layer thickness of the secondlayer and, where appropriate, also to further optional layers and to themass of the selected ions.

In an especially advantageous further feature of the invention, themaximum damage will lie within the second layer, especially at adistance d₆ from the first layer and not in the first layer itself. Thisapplies especially for ions which give rise to bubble formation or crackformation like, for example, helium, fluorine, neon, argon and so forth.

Advantageously with an Si implantation be comparison to implantationwith very light ions like for example hydrogen ions or helium ions, thedose can be significantly reduced, that is by a factor of 10 to 100.This shortens advantageously the implantation duration and increases thewafer output significantly. With the goal of achieving a higher degreeof relaxation, it is possible, however, also to carry out defectformation by means of two or more implantations in the first layer andin the second layer independently from one another. An advantageous modeof operation is also to carry out first one or more implantations withdifferent energies, possibly also with different ions in the first layerat reduced doses and to create the defect regions in the second layerwith a second implantation. The production of point defects in the firstlayer to be relaxed gives rise to accelerated diffusion and to morerelaxation.

The ion implantation can be carried out over the entire area of thesubstrate or, by the use of an implantation mask, for example a photolacquer, at optionally selected location on the wafer.

In a further feature of the invention, the wafer is not tilted at anangle of 7° for the ion implantation as is known from the state of theart. Rather, the wafer is tilted at an angle greater than 7° from thenormal, especially to an angle of 30° to 60°.

This makes it possible to produce strained and nonstrained layers oneafter the other upon the wafer while insuring planarity. This ispossible since the subsequent thermal treatment can be carried out witha thermal budget which is so small that nonimplanted regions of thefirst layer are not relaxed or are scarcely relaxed and so that thelayer to form the strained layer is also not changed at these locations.

It is especially advantageous to match the implantation mask to thelayout of the electronic component or its insulation regions. Only theregions where for example strained silicon is required for thecomponents are implanted.

Advantageously, the first layer is scarcely damaged or not damaged atall by the implantation which is thus carried out. The optimal dose andenergy and ion type does not depend upon the composition and layerthickness of the first layer to be relaxed and thus can be simplyoptimized when the implantation takes place in the second layer.

After removal of the first layer and optionally the second layer andfurther optional layers, one obtains the desired strained layer orunstrained regions of this layer at the nonimplanted locations with thesame layer thickness, thereby maintaining planarity throughout.Advantageously, the first layer applied thereon at least in the lastpart of the removal phase is selectively removed by a wet chemicalprocess.

The transition regions between strained and unstrained portions areadvantageously configured as insulation regions between the electroniccomponents.

It is especially advantageous when silicon dioxide is selected as theinsulation material. In a further feature of the invention instead of anexclusive first layer, i.e. only the first layer on the layer to formthe strained layer, a layer system of multiple layers is used.

Upon the strained regions which are produced, further epitactic layerscan be deposited in order, for example, to increase the layer thicknessof the strained region or to match the thickness locally of the wafer orto apply new layers, for example, in order to realize more complexelectronic or optoelectronic components.

With the method according to the invention, a strained layer can beproduced it advantageously has an extremely small surface roughness,usually of less than 1 nm and only a limited defect density of less than10⁷ cm⁻², especially less than 10⁵ cm⁻⁵.

The limited roughness is especially advantageous for the production ofMOSFETs in which a thermal oxide or another dielectric, for example, ahigh-k dielectric, that is a material with high dielectric constant,must be produced on the strained layer. The surface roughness has anexceptionally sensitive effect on the electrical quality of thedielectric which is the heart of a transistor. The mobility of thecharge carries also is determined to a significant extent by the natureof the interface in a very thin layer. The surface roughness of forexample strained silicon can be reduced by the growth of a thermal oxidethereon even further. This thus produced oxide can be removed prior tothe growth or deposition of the gate dielectric on the strained layer.

The method in a further and especially advantageous feature of theinvention offers the potential for a further reduction in thedislocation density in the relaxed and the strained layers.

This can be achieved by the etching of trenches in the coating with aspacing of the order of micrometers, for example, 1 to 100 micrometer oradvantageously, by trench etching, matching the electric componentstructures and subsequent heat treatment at temperatures above 500° C.Threading dislocations in the layer slip to the edge of this region andare thereby healed. These etched trenches can however also be used toproduce so-called shallow trench insulation. For this purpose, thetrench is filled with insulator material and so separates electroniccomponents from one another electrically.

A further suitable method of reducing the defect density is theapplication of a counter or oppositely strained layer upon the relaxedfirst layer after that layer has been partially relaxed by implantationand thermal treatment. For the further relaxation of for example anSi—Ge layer a compression strained layer, for example, a silicon nitridelayer (for example 100 nm) is deposited in a PE-CVD reactor. Asubsequent thermal treatment, for example, by tempering or heat treatingin an inert or reactive atmosphere, produces a higher level ofrelaxation of the Si—Ge layer and thus a greater level of tension of theSi layer which is to be dimensioned. Simultaneously the dislocationdensity is reduced. This method can also be applied to previouslystructured surfaces.

The production of a system on a chip, that is various electroniccomponents with different functions in a single plane is thusadvantageously possible within the scope of the invention. As hasalready been indicated, with the invention strained and nonstrainedportions of a layer can be made while insuring the planarity thereof.This enables the production of special electronic components/circuitelements with strained or nonstrained regions of for example silicon.These especially very thin layers can be locally reinforced or amplifiedby further deposition, for example, also be selective deposition, inorder to fabricate for example contacts for the source and drain,so-called so raised source and drain source to make power components.

The second layer also, for example, a strained Si—Ge layer, can be usedin the nonimplanted regions for the production of special components forexample especially advantageously for p-MOSFETs, since these layersdepend upon the germanium content and can have especially high holemobilities which are 2 to 3 times greater than those of silicon.

For the production of, for example, p and n channel MOSFETs, the thusmade strained Si layers are advantageously used since the electronmobility and the whole mobility in the tetragonal lattice of thestrained silicon is higher by about 100% to about 30% than that of theunstrained silicon when the lattice strain is greater than 1%. Thus oneis not bound to particular transistor types or components. MODFETs,resonant tunnel diodes, photodetectors and quantum cascade lasers can berealized.

In the following, the invention is described in greater detail inconnection with examples or embodiments and the accompanying figures.They show:

FIG. 1: a schematically illustrated layer system comprising an SOIsubstrate 1, 2, 3 and a first epitactically applied layer 4 and a secondepitactically applied layer 5.

FIG. 2: a schematically illustrated layer system comprising an SOIsubstrate 1, 2, 3 and a epitactically applied layer structure with animplantation mask 6 and a defect region 7 in the second layer 5.

FIG. 3: a schematically illustrated layer system comprising an SOIsubstrate 1, 2, 3 and an epitactically applied layer structurecomprising a further optional protective layer 8.

FIG. 4: a schematically illustrated layer system comprising an SOIsubstrate 1, 2, 3 with a strained region 9 adjacent a nonstrained region3 on an insulator layer 2.

FIG. 5: a schematically illustrated layer system with an additionalepitactic layer 10 which is epitactically applied to the strained andnonstrained regions 9 and 3.

FIG. 6: an alternative schematically illustrated layer structure withthree layers 11, 12, 13 applied to the layer 3 to be strained, layer 11serving as an additional buried layer to be strained or as an etch-stoplayer.

FIG. 7: a schematically illustrated layer system with an insulationregion 14 (shallow trench insulation) between strained region 9 andunstrained region 3.

FIG. 8: a schematically illustrated layer system as in FIG. 1 withetched trenches 15.

FIG. 9: a schematic illustration of a MOSFET on a strained Si layer witha gate stack and raised source and drain and a silicide contact on aninsulator. To the right of the transistor an unstrained silicon layer 3can be seen and to the left a strained Si—Ge layer 11 on an unstrainedSi layer 3.

First embodiment or example: Production of a strained Si layer on SiO₂with helium ion or hydrogen implantation and heat treating.

As illustrated in FIG. 1, a first epitactic Si—Ge layer 4 with 22 atomic% and a layer thickness d₄ of 220 nm is deposited in a defect free orclose to defect free state by gas phase epitaxy or molecular beamepitaxy on a silicon surface layer 3 of a thickness d₃ of 20 nm on anSOI substrate 1, 2, 3 (SIMOX or BESOI). Then as the second layer 5monocrystalline silicon is applied with a thickness d₅ of 500 nm.

The layer structure 1, 2, 3, 4, 5, after application of a mask 6 (FIG.2) is implanted with helium ions with an energy of 20 keV and a dose of1.5×10¹⁶ cm⁻¹ and then different or heat treated at 850° C. for 10 min.Alternatively, the structure can also be implanted with hydrogen ionswith a dose of 2×10^(16×)cm⁻². Through the implantation a defect region7 is formed in layer 5 close to the interface (d₆ amounted to about 200nm) with the Si—Ge layer 4, which contributed to the relaxation of theSi—Ge layer in this region during the heat treatment whereas the stressstate of the nonimplanted regions was not altered or not significantlyaltered. The degree of relaxation in the Si—Ge layer amounted to about75% after the heat treatment or tempering.

Optionally, layer 8 of silicon dioxide with a thickness of, for example,500 nm can be deposited before or after the implantation. For thispurpose, it is advantageous to avoid the formation of blisters on thesurface by the hydrogen or helium bubble formation during the thermaltreatment (FIG. 3).

In order to increase the degree of relaxation, starting from the layerstructure of FIG. 3, the layer 5 or the layer 8 is removed and a siliconnitride (SiN_(x)) layer which is under compressive stress with thethickness of about 100 nm, is deposited on the partially relaxed Si—Gelayer 4 (not shown). This SiN_(x) layer can be deposited by means ofPE-CVD (plasma enhanced chemical vapor deposition). A second thermaltreatment of the layer structure at 900° C. for 10 min increases thedegree of relaxation at the implanted location to in excess of 80% andthe Si layer 9 is again strained.

The further etching of the layer 4 frees the Si layer 3 (FIG. 4) and canbe used for the production of high speed electronic components. Belowthe implanted region, the layer 9 is strained. The threading dislocationdensity is smaller than 10 ⁷ cm⁻².

To match the layer thickness to the requirements for the electroniccomponents, a layer 10 (FIG. 5), for example, of silicon, which has athickness which does not exceed the critical layer thickness, isepitactically deposited. It must be observed in this connection that thestress state changes along the layer 10 as has been indicated by thedifferent hatching of the layer 10. This is dependent upon theunderlying layers. On strained silicon 9, the silicon 10 grows in astressed state to the critical layer thickness. Instead of a siliconlayer any other layer or layer sequence can be deposited.

Second embodiment or example: production of a strained Si layer on SiO₂with high stress.

The layer formation is carried out in the first example according toFIG. 1.

Instead of a constant composition of the first layer 4, on the layer 3to be strained of an SOI substrate 1, 2, 3 (or one having a carboncontent in an Si—C layer), a graded layer 4 with a stronglynonhomogeneous concentration gradient is deposited. Only optionally isthe second layer 5 applied.

It is advantageous for the growth of the layer 4 to begin with a higherGe concentration (for example 40 atomic % Ge) and possibly even withpure germanium to a thickness of several nm, and then to reduce theconcentration during the growth to, for example, 20 atomic % so that alayer thickness of 150 nm can be achieved without the formation ofdislocations in a detrimental density during the growth. Optionally theGe concentration can gradually be lowered continuously or in steps inprinciple to zero, is lowered over the substantially large layerthickness so that no second layer 5 need be deposited. For a symmetricalstress buildup in the layer 4, a U-shaped concentration pattern can alsobe used, that is first there can be a drop-off and then a rise in thegermanium content in the growth direction. A layer with nonhomogeneousconcentration leads to higher relaxation rates and small defectdensities then equivalent homogeneous layers. The layer thickness d₄should be as large as possible but however in all cases should lie belowthe critical layer thickness so that during the growth no noticeablerelaxation occurs.

Third embodiment or example: Si implantation instead of implantationwith light ions.

As an alternative to implantation or light ions, an Si implantation canbe effected for example with an energy of 150 kev and a dose of about1×10¹⁴ cm⁻² in a 500 nm thick Si layer 5 (FIG. 2). The implanted Si ionsgenerate crystal defects in the second layer 5 and in the Si—Ge layer 4which upon relaxation and thus straining of an Si layer 3, renders anSOI substrate 1, 2, 3 suitable.

Then the system is subjected to a thermal treatment for several minutesat 900° C. in an inert nitrogen atmosphere or in vacuum. Theimplantation energy and dose are optimized by measuring the degree ofrelaxation and the defect density. Optionally two or more implantationscan be carried out with other ions as well in order to produce defectregions in the layer 5 and point defects in the layer 4 to be relaxed.Another inert gas, for example, argon or a gas which is suitable for thepurposes of the invention during thermal treatment, for example, O₂ orformer gas can be used.

Fourth example or embodiment: production of two or more strained layersin a layer structure on an SOI substrate 1, 2, 3 is (FIG. 6).

On an SOI substrate 1, 2, 3 with a 10 nm thick Si surface layer 3, thefollowing layer system is epitactically deposited: a 25 nm Si—Ge layer11 with 22 atomic % Ge, a 10 nm thick Si layer 12, an 150 nm thick Si—Gelayer 13 with 22 atomic % Ge (germanium), a 400 nm thick Si layer 5(FIG. 6).

Optionally several thin silicon layers can be disposed in the Si—Ge.

Then optionally an implantation mask, for example, a photo lacquer 6, isapplied and lithographically structured so that the following ionimplantation is carried out only in the noncovered regions. In thiscase, the layer is implanted with hydrogen (3×10¹⁶ cm⁻²) or helium ions(2×10¹⁶ cm⁻²) to create a defect region approximately in the center ofthe 400 nm thick Si layer 5 (not shown). The thermal treatment waseffected at 825° C. in nitrogen.

In the region not masked by mask 6, after implantation and thermaltreatment, the following layer structure is obtained. Beneath thesilicon layer 5, there is a relaxed region of the layer 13 on thestrained region of the layer 12. This region of the layer is 12 is inturn disposed on a relaxed region of the layer 11 and this in turn isdeposited on a strained region of the layer 3 (FIG. 6). Layer 3represents the surface of the SOI substrate.

After removal of the silicon layer 5 and the Si—Ge layer 13, one obtainson the implanted region a strained silicon layer 12 (10 nm thick) on arelaxed Si—Ge layer 11, here 25 nm thick (no longer shown in the righthand portion of the illustration since it has been removed by etching)and a second strained Si layer 9 on the SiO² layer 2 of the SOIsubstrate 1, 2, 3 (see FIGS. 6 and 7).

In the nonimplanted regions below the mask, the strain state of thelayers 3, 11 and 12 are not altered or are not significantly altered.Layer 3 and layer 12 have as previously, a cubic silicon structure andthe Si—Ge layer is tetragonally stressed (FIG. 7). This layer structurecan be used as is for producing electronic components or can havefurther layers deposited thereon. Each of the layers can have in asingle plane of the layer mentioned, without step formation, a strainedregion and an unstrained region of the same layer material.

Alternatively, the 10 nm thick Si layer 12 can also serve as anetch-stop layer so as to reduce the surface roughness after the etchingto less than 1 nm. This is especially important for is the strainedlayer 9 on the SiO₂ layer 2 since on this strained layer, the gatedielectric for a MOSFET is applied or is thermally generated. Purity andinterfacial characteristics determine decisively the quality of thedielectric.

Insulation regions 14 (shallow trench) can be produced in the strainedregion 9 by etching and filling with insulation material.

Fifth example or embodiment: Reduction of the defect density by etchtrenching 15 and thermal treatment and production of insulating regions14.

Analogously to the preceding examples or embodiments, one or two or morestrained layers are produced. In these layer structures, etched trenches15 (FIG. 8 and FIG. 7 before the production of the shallow trench 14)are made. These trenches 15 are as a rule etched up to the insulatorlayer 2 so that simple insulation regions (shallow trench insulation)can be produced between the components by filling the trenches with aninsulator 14 (as in FIG. 7). After the etching a thermal treatment iscarried out at a temperature above 450° C., advantageously above 650° C.This thermal treatment has the effect that threading dislocations inlayer 4, an Si—Ge layer, and in the strained layer 9 run to the trenches15 and are thus healed. It can be advantageous to remove the secondlayer 5 prior to the etching of trenches 15 so that the healing of thedislocations is not hindered by the layer 5. Furthermore, the thermaltreatment can also be effected later during fabrication of the electriccomponents and thus simultaneously can serve to heal defects followingion implantation or developing upon growth of the gate dielectric.

Sixth example or embodiment: Strained silicon on SiO₂ substantially in acommon plane with strained Si—Ge layer and the fabrication of n- andp-MOSFET components.

A layer structure corresponding to that of FIG. 6 is used to firstproduce the strained layers. After the removal of layer 5 and the Si—Gelayer 13, the layers 12 and 11 can be selectively removed, for example,at the implanted region by wet chemical treatment. The result is astrained silicon surface layer 9 (FIG. 7) adjacent an unstrained Silayer 3 on a thin strained Si—Ge layer 11 shown at the left hand part ofthe figure (nonimplanted region of the layer 11) approximately in asingle plane. The step height between these regions is determined onlyby the thickness of the layers 11 and 12 (a total of the 35 nm). Thisstep height is smaller than the depth of field of the lithographicprocess so that further lithographic steps can be carried out withoutdifficulty. The regions can be electrically and structurally separatedfrom one another by insulation regions 14 (FIG. 7).

The result is an optimal structure for a MOSFET electric component. Onthe regions with strained silicon 9, ultrafast n- and p-channel MOSFETscan be produced since the electron and hole mobilities in the tetragonallattice of the strained silicon is increased by about 100% or about 30%by comparison to unstrained silicon when the lattice stress is greaterthan 1% (>1%). On the strained Si—Ge layer 11 of FIG. 7 or on thesilicon layer 12, p-channel MOSFETs can advantageously be made since theSi—Ge layer is particularly suitable because of the greatly enhancedhole mobility and small overall thickness of the layers 3, 11 and 12 ofabout 45 nm (FIG. 7) allows the production of fully depleted MOSFETs.

The thin Si layer 12 can be used advantageously for producing the gatedielectric since a high quality thermal oxide or oxynitride can beformed thereon as the gate dielectric. Advantageously, it is alsopossible to produce the gate dielectric simultaneously on the variousregions thermally or by deposition.

Furthermore, on the nonimplanted regions after selective removal of theSi—Ge layer 11, conventional Si based electric components can berealized. The thin Si layer 12 of FIG. 7 can be used as a template for afurther, preferably selective, epitaxy of silicon. In that manner,optimal conditions for achieving very different electronic components ona chip can be provided (system on a chip).

Seventh example or embodiment: Strained silicon on SiO₂ with the aid ofan Si—Ge/Si—C/Si—Ge layer sequence on an SOI structure.

On a SOI substrate with a thin Si surface layer with a thickness of 5 nm(or 15 nm) at least three epitactic layers are deposited comprised of afirst 80 nm thick Si—Ge layer (20at % Ge), a second 10 nm thick Si—Clayer with 0.75% C and a further 80 nm thick Si—Ge layer (20at % Ge). Byanalogy to FIG. 3, a defect region is produced in the intermediate layerof Si—C while the subsequent thermal treatment at 1000° C. is providedfor relaxation of the overlying and underlying Si—Ge layers. The carbonis incorporated in the thin Si—C layer in sufficient concentration. Withthe thermal treatment at 1000° C., a defect region is formed in the Si—Clayer which facilitates the relaxation of the overlying and underlyingSi—Ge layers. The Si—Ge layers relax to 90%. Correspondingly, the thinSi layer of the SOI substrate is elastically strained and a strained Silayer on SiO₂ is produced.

Eighth example or embodiment: In the place of a first layer, a layersystem is used which is comprised of a thin layer, a compositionallydifferent layer 11 (for example an Si—C or Si—Ge layer with a differentconcentration) and a further silicon layer 12 and a layer 13 (SiC orSi—Ge) (FIG. 6). For the overall layer thickness these three layerssatisfy the same criteria as the first layer 4. Layer 12 can either betransformed to a strained layer or used simply as an etch stop layer.The use of an additional etch stop layer can limit surface rougheningduring the back etching practically completely since then in the lastetching step only a very small layer thickness (layer 11) must beremoved before layer 3 or layer 9 is exposed. Layers 4, 11 and 13 canhave optional concentration profiles to minimize the defect/densitythrough relaxation.

The method offers in a further and especially advantageous configurationof the invention, the potential for a further reduction in the defectdensity in the relaxed and strained layer. This can be achieved by theetching of trenches 15 in the layers 5, 4 and 3 (layer 5 can previouslyhave been removed) with spacings in the micrometer (1 to 100 μm) rangeor advantageously by trench etching which is matched to the electroniccomponent structures (FIG. 10), and subsequent heat treatment attemperatures above 450° C., especially above 650° C.

A further suitable method for reducing the dislocation density is theapplication of a strained layer on layer 4, following which this isrelaxed in large part by implantation and thermal treatment. For furtherrelaxation of an Si—Ge layer, a compression stressed layer, for example,a silicon nitride layer (for example 100 nm) can be deposited thereon ina PE-CVD reactor. A subsequent thermal treatment (tempering in an inertor reactive atmosphere) produces a higher relaxation of the Si—Ge layerand thus an increased strain of the Si layer. Simultaneously thedislocation density is reduced. This method can also be used on apreviously structured surface (FIG. 7).

FIG. 9 shows a MOSFET with silicide contact 16 (for example a sourcecontact), the gate dielectric 17, the gate contact 18 of, for example,poly-Si or metal, the gate contact 19, for example of silicide, thespacer insulation 20, the silicided drain contact 21 and the raiseddrain contact 22 (highly doped Si or Si—Ge).

REFERENCE CHARACTER LIST

-   1. Silicon.-   2. SiO₂.-   3. Layer to be strained with a layer thickness d₃.-   4. Epitactic layer, optionally with a concentration gradient    (graded), with a layer thickness d₄, which is relaxed during the    process.-   5. Epitactic layer 5 (for example silicon) with layer thickness d₅.-   6. Mask.-   7. Defect region that for example is produced by ion implantation.    The maximum of the range of the ions is at a distance d₆ from the    interface of the layers 4 and 5. In the case of hydrogen ions and    helium ions, platelets, bubbles or microcracks arise in at this    depth which form the defects, like dislocations.-   8. Protective layer, for example SiO₂.-   9. Strained layer or region, for example strained silicon.-   10. Epitactic layer which is deposited on the nonstressed layer 3 or    the stressed layer 9 for example of silicon or Si—Ge—C or Si—C. By    deposition of silicon, the layer thickness of the strained silicon    is increased.-   11. Epitactic layer, for example Si—Ge, Si—C or Si—Ge—C which is    relaxed.-   12. Thin epitactic layer which can be strained or can serve as an    etch-stop layer, for example of silicon.-   13. Epitactic layer, for example graded, which is to be relaxed, for    example, Si—Ge or Si—C or Si—Ge—C.-   14. Shallow trench insulation, a trench etched and filled with    insulating material 15.-   15. Etched trench with a depth of up to the insulating layer 2 of    the SOI substrate 1,2,3.-   16. Silicide contact, for example source.-   17. Gate dielectric.-   18. Gate contact, for example, poly-Si or metal.-   19. Gate contact, for example, silicide.-   20. Insulation.-   21. Silicide drain contact.-   22. Raised drain contact (highly doped Si or Si—Ge).

1. A method of producing a strained layer (9) on a substrate (1, 2) withthe steps: producing a defect region (7) in a layer (2, 4, 5, 11)neighboring a layer (3) to which strain is to be imparted, relaxing atleast one layer (4, 11) neighboring the layer (3) to which strain is tobe imparted.
 2. The method according to claim 1 in which dislocationsare formed which give rise to relaxation of at least one neighboringlayer (4, 11) of the layer (3) which is to be strained.
 3. The methodaccording to one of the preceding claims characterized in that the layerstructure, for relaxation, is subjected to a thermal treatment and/oroxidation.
 4. A method according to one of the preceding claimscharacterized in that at least one first layer (4; 11) is deposited uponthe layer (3) to be strained.
 5. The method according to one of thepreceding claims characterized in that the first layer (4, 11) has adifferent degree of stress than the layer (3) to be strained.
 6. Themethod according to one of the preceding claims characterized in thatthe defect region (7) is produced in the first layer (4; 11).
 7. Themethod according to one of the preceding claims in which a furtherrelaxing layer is disposed between the substrate (1, 2) and the layer(3) to be strained.
 8. The method according to one of the precedingclaims characterized in that the defect region (7) is produced in thesubstrate.
 9. The method according to one of the preceding claimscharacterized in that the defect region (7) is produced in the layer (3)to be strained itself.
 10. The method according to one of the precedingclaims characterized in that two neighboring layers (11, 13) of thelayer (12) to be strained have other degrees of dislocation than thelayer (12) to be strained.
 11. The method according to one of thepreceding claims in which a plurality of layers (11, 13) are relaxed.12. The method according to one of the preceding claims in which aplurality of layers (3, 12) to be strained, have strain imparted tothem.
 13. The method according to one of the preceding claimscharacterized in that on the first layer (4, 11) epitactically at leastone further layer (5; 12, 13) with respectively a different latticestructure is deposited.
 14. The method according to one of the precedingclaims characterized in that the defect region (7) is produced in thesecond layer (5; 13).
 15. The method according to one of the precedingclaims characterized in that on the layer to which strain is to beimparted (3) at least one graded layer is deposited as the first layer(4).
 16. The method according to one of the preceding claimscharacterized in that at the region of the layer (3) to be strained, thegraded layer (4) has a degree of dislocation which is different fromthat of the layer (3) to be strained.
 17. The method according to one ofthe preceding claims characterized in that a defect region (7) isproduced in a graded layer (4).
 18. The method according to one of thepreceding claims in which an epitactic layer structure comprising aplurality of layers is produced on a substrate (1, 2, 3, 4, 5, 11, 12,13) in a deposition process.
 19. The method according to one of thepreceding claims in which the first layer (4, 11) is relaxed by athermal treatment.
 20. The method according to one of the precedingclaims characterized in that for the thermal treatment a temperaturebetween 550 degrees and 1200 degrees C. is selected.
 21. The methodaccording to one of the preceding claims characterized in that for thethermal treatment, a temperature between 700 degrees and 980 degrees C.is selected.
 22. A method according to one of the preceding claimscharacterized in that the thermal treatment is carried out in an inertatmosphere.
 23. The method according to one of the preceding claimscharacterized in that the thermal treatment is carried out in a reducingor oxidizing or nitriding atmosphere and especially in nitrogen.
 24. Themethod according to one of the preceding claims characterized in thatthe relaxation is carried out over a limited region of a layer.
 25. Themethod according to one of the preceding claims in which a mask (6) isapplied.
 26. The method according to one of the preceding claimscharacterized in that the defect region (7) is produced by ionimplantation.
 27. The method according to the preceding claimcharacterized in that for the implantation, hydrogen ions or helium ionsare selected.
 28. The method according to one of the preceding claimscharacterized in that the hydrogen ions or helium ions are implantedwith a dose of 3×10¹⁵ to 4×10¹⁶ cm⁻², especially with a dose of 0.5×10¹⁶to 2.5×10^(16 cm) ⁻².
 29. The method according to one of the precedingclaims characterized in that for the implantation, Si ions are selected.30. The method according to the preceding claim characterized in that Siions are implanted with a dose of about 0.5×10¹⁴ to 5×10¹⁴ cm⁻².
 31. Themethod according to one of the preceding claims characterized in thatfor the implantation, carbon ions, nitrogen ions, fluorine ions, boronions, phosphorous ions, arsenic ions, germanium ions, antimony ions,sulfur ions, neon ions, argon ions, krypton ions and/or xenon ions areselected.
 32. The method according to one of the preceding claimscharacterized in that at least two implantations are carried out. 33.The method according to one of the preceding claims characterized inthat a hydrogen implantation is carried out in combination with a heliumimplantation.
 34. The method according to one of the preceding claimscharacterized in that a boron implantation is carried out in combinationwith a hydrogen implantation.
 35. The method according to one of thepreceding claims, characterized in that two implantations are carriedout to produce two defect regions in the first layer (4) and in thesecond layer (5).
 36. The method according to one of the precedingclaims characterized in that the wafer during the ion implantation istilted at an angle greater than 7 degrees, especially at an angle of 30to 60 degrees.
 37. The method according to one of the preceding claimscharacterized in that between two implantations a thermal treatment iscarried out.
 38. The method according to one of the preceding claimscharacterized in that the defect region (7) is produced by a change inthe temperature during the formation of one of the layers (4, 5; 11).39. The method according to one of the preceding claims characterized inthat the defects are produced in a Si—C layer by thermal treatment. 40.The method according to one of the preceding claims characterized inthat as the substrate, an amorphous layer, especially of an insulator(2) is selected.
 41. The method according to one of the preceding claimscharacterized in that an SOI substrate (1, 2, 3) is chosen as the basestructure for the substrate.
 42. The method according to the precedingclaim characterized in that the silicon surface layer (3) of the SOIsubstrate (1, 2, 3) is the layer (3) to be strained and the SiO₂ of theSOI substrate (1, 2, 3) forms the insulator (2) on the substrate (1).43. The method according to one of the preceding claims characterized inthat an SIMOX or BESOI substrate is selected as the base structure forthe substrate.
 44. The method according to one of the preceding claimscharacterized by selecting a silicon on sapphire as the base structurefor a substrate.
 45. The method according to one of the preceding claimscharacterized by selecting a substrate that becomes viscous at atemperature required for the relaxation.
 46. The method according to oneof the preceding claims characterized in that SiO₂, glass, SiC, Si—Ge,graphite, diamond, quartz glass, GdGa-garnet, III-V semiconductor andIII-V nitride are selected as the material for the substrate (1, 2). 47.The method according to one of the preceding claims in which aninsulator (2) on a substrate (1) is selected.
 48. The method accordingto one of the preceding claims characterized by the selection of Si—Geor Si—Ge—C or Si—C as the material for the first layer which is disposedon the layer (3) to be strained.
 49. The method according to one of thepreceding claims characterized by the selection of silicon as thematerial for the layer (3) to be strained.
 50. The method according toone of the preceding claims characterized by the choice of silicon asthe material for the second layer (5) which is disposed upon the firstlayer (4).
 51. The method according to one of the preceding claimscharacterized by the selection of Si—Ge as the material for a gradedlayer.
 52. The method according to the preceding claim characterized inthat the germanium concentration in the graded layer decreases from theinterface with the layer (3) to be strained to the surface of the gradedlayer.
 53. The method according to one of the preceding claimscharacterized in that the germanium concentration in a Si—Ge layer atthe interface with the layer (3) to be strained is 100 percent.
 54. Themethod according to one of the preceding claims characterized in thatthe total layer thickness of the layer structure is so selected thatduring the growth of the applied layers (4; 11, 13) these do not produceany noticeable relaxation.
 55. The method according to one of thepreceding claims characterized in that the dislocation density after thegrowth amounts to less than 10⁵ cm⁻².
 56. The method according to one ofthe preceding claims, characterized in that a layer (3) to be strainedwith a thickness d₃ in the range of 1 to 50 nanometers is selected. 57.The method according to one of the preceding claims, characterized inthat a layer (3) to be strained with a thickness d₃ in the range of 5 to30 nanometers is selected.
 58. The method according to one of thepreceding claims, characterized in that a first layer (4) with athickness d₄ close to the critical layer thickness is selected.
 59. Themethod according to one of the preceding claims, characterized by theselection of a layer thickness ratio d₄/d₃ of greater than about
 10. 60.The method according to one of the preceding claims, characterized inthat a second layer (5) with a thickness d₅=50-1000 nanometer isselected.
 61. The method according to one of the preceding claims,characterized in that a second layer (5) with a thickness d₅=300-500nanometer is selected.
 62. The method according to one of the precedingclaims in which the layer (3) to be strained is locally strained. 63.The method according to one of the preceding claims characterized inthat the layer (3) to be strained is locally strained in the regionswhich are vertical in a plane with the defect region.
 64. The methodaccording to one of the preceding claims characterized in that thedefect region (7) is produced at a spacing of 500 nanometers from thelayer to be relaxed.
 65. The method according to one of the precedingclaims characterized in that the defect region (7) is arranged at aspacing of 50 to 100 nanometers above the layer (4) arranged upon thelayer (3) to be strained.
 66. The method according to one of thepreceding claims characterized in that the first and second layers (4,5; 11, 12, 13) after producing the strained layer (9) or after producinga strained region, are removed.
 67. The method according to one of thepreceding claims in which etching, especially wet chemicalmaterial-selective etching, is used.
 68. The method according to one ofthe preceding claims in which etched trenches (15) are produced in thedepth of the layers (2, 3, 4, 5, 9, 11, 12, 13).
 69. The methodaccording to one of the preceding claims characterized in that afterproducing the etched trenches (15) a relaxation of the layer (4; 11) ora further layer, especially by a thermal treatment, is carried out. 70.The method according to one of the preceding claims characterized inthat the trenches (15) are filled with insulating material to produceshallow trench insulation (14).
 71. The method according to one of thepreceding claims characterized in that at least one further thermaltreatment is carried out for relaxation of one or more layers.
 72. Themethod according to one of the preceding claims characterized in that astrained layer (9) and/or an unstrained layer (3) are produced with asurface roughness of less than 1 nanometer.
 73. The method according toone of the preceding claims characterized in that a surface roughness oflayers (3, 9) is further reduced by the growth of a thermal oxidethereon.
 74. The method according to one of the preceding claimscharacterized in that on a strained region of the layer (9) and n-and/or p-MOSFET is produced.
 75. The method according to one of thepreceding claims characterized in that a further epitactic layer (10)comprising silicon or silicon/germanium (Si—Ge) or an Si—Ge—C layer or agermanium layer are deposited.
 76. The method according to one of thepreceding claims characterized in that on a strained silicon-germanium(Si—Ge) region (11) p-MOSFETs are produced as further epitactic layersor as nonrelaxed layers structures.
 77. The method according to one ofthe preceding claims characterized in that on unstrained region (3) ofthe layer 3 to be strained, bipolar transistors are processed.
 78. Themethod according to one of the preceding claims characterized in thatfor producing a bipolar transistor, a silicon-germanium layer isapplied.
 79. The method of producing a layer structure comprising aplurality of strained layers, characterized in that one or more of themethod steps in claims 1-78 is carried out a plurality of times.
 80. Alayer structure comprising a layer (9, 3) on a substrate (1, 2),characterized in that the layer (9, 3) is partly strained.
 81. The layerstructure according to the preceding claim characterized in that thestrained region (9) of the layer (9, 3) lies in a plane and is coplanarwith and adjacent the unstrained region (3) of the layer (9, 3).
 82. Thelayer structure according to one of the preceding claims 80 or 81 inwhich the at least one relaxed layer (4, 11) is arranged above and/orbelow at least one strained layer (9).
 83. The layer structure accordingto one of the preceding claims 80-82 characterized in that without theformation of a step between them, a strained region and an unstrainedregion of the same layer material lie in coplanar relationship in aplane of the layer.
 84. The layer structure according to one of thepreceding claims 80-83 characterized by an insulator (2) as thesubstrate.
 85. The layer structure according to one of the precedingclaims 80-84 characterized in that strain layer (9) and/or theunstrained layer (3) have a defect density smaller than 10⁷ cm⁻². 86.The layer structure according to one of the preceding claims 80-85,characterized in that the strained layer (9) and/or the unstrained layer(3) have a defect density smaller than 10^(5 cm) ⁻².
 87. The layerstructure according to one of the preceding claims 80-86, characterizedin that at least one strained layer (9) and/or at least one unstrainedlayer (3) have a surface roughness of less than 1 nanometer.
 88. Thelayer structure according to one of the preceding claims 80-87,characterized in that on the strained layer (9) and/or the unstrainedlayer (3) further epitactic layers (10, 11, 12, 22) are arranged. 89.The layer structure according to one of the preceding claims 80-88,characterized in that in the strained region (9) an insulation region(14) is located.
 90. An electronic component comprised of a layerstructure according to one of the preceding claims 80-89.
 91. Atransistor especially a modulated doped field effect transistor (MODFET)or a metal oxide semiconductor field effect transistor (MOSFET) formsthe component according to claim
 90. 92. A fully depleted MOSFET as thecomponent according to claim
 90. 93. A tunnel diode, especially asilicon germanium (Si—Ge) tunnel diode as the component according toclaim
 90. 94. A silicon-germanium quantum cascade laser as the componentaccording to claim
 90. 95. A photo detector as the component accordingto claim
 90. 96. A light emitting diode as the component according toclaim 90.